1. Field of the Invention
This invention relates generally to data processing systems and more particularly to data processing systems capable of executing floating point operations.
2. Description of the Related Art
In data processing systems, the floating point data format, in which a number is represented by an operand exponent argument designating the power to which the exponent base is raised and an operand fraction which is the multiplier of the exponential portion of the number, is frequently used to permit an expansion of the range of numbers capable of being processed by the system. The floating point number frequently uses an independent execution unit and calculations by the execution unit can limit the performance of the data processing unit.
Addition and subtraction procedures are the most commonly used floating point procedures, however, their execution requires a relatively intricate sequence of operations. The addition and subtraction procedures 101, as illustrated in FIG. 1, can be divided into two effective procedures, 102 and 103. The effective addition procedure 102 includes the addition procedure in which the signs of the operand fractions are the same and the subtraction procedure in which the signs of the operand fractions are different. The effective subtraction procedure 103 includes the addition procedure in which the signs of the operand fractions are different and the subtraction procedures in which the signs of the operand fraction are the same.
Referring to FIG. 2, the typical steps involved in implementing the effective subtraction operation 103, are indicated. In step 201, the difference between the operand exponent arguments is calculated. Based on this calculation, the operand exponent arguments must be made equal prior to performing the difference calculation and the operand fractions are correspondingly aligned in step 202. In step 203, the aligned operand fractions are subtracted and in step 204, the negation or determination of the two's complement is implemented when necessary. In step 205, the detection of the leading one (most significant non-zero) position is determined and based on the leading one determination, the resulting operand fraction is normalized, i.e., the resulting operand is shifted until a non-zero signal is in the most significant position. The resulting operand exponent argument must be adjusted in accordance with the normalization step. Where necessary, the resulting operand fraction is rounded off in step 207.
A floating point processor capable of performing the procedures and operations disclosed herein is described in "The MicroVAX 78132 Floating Point Chip" by William R. Bidermann, Amnon Fisher, Burton M. Leary, Robert J. Simcoe and William R. Wheeler; Digital Technical Journal, No. 2; March, 1986, pages 24-36.
The present invention relates to two steps in FIG. 2. In step 202, the alignment of fractions, the alignment is provided by shifting one of the operand fractions. In this shifting operation, a non-zero bit position may be removed from the operand fraction field. The subsequent subtraction operation can be inherently inaccurate if information regarding this bit (or these bits), typically referred to as a "sticky" bit, is not used in the subtraction operation. In step 205, the most significant non-zero bit position of the interim operand fraction must be identified and shifted to the most significant operand fraction position for the normalization of the operand fraction. In the past, each of these functions has been performed by separate apparatus. This implementation by two pieces of apparatus requires a relatively large number of elements and uses a large area on a semiconductor chip on which the floating point processor is fabricated.
A need has therefore been felt for a technique of performing the "sticky" bit computation and for determining the leading one position of an operand fraction using a reduced amount of apparatus.